-- Desplazador a Derecha

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity desplazadord is
port(a: in std_logic_vector(7 downto 0);
     dif: in std_logic_vector(7 downto 0);
     b: out std_logic_vector(7 downto 0));
end desplazadord;

architecture behavior of desplazadord is
signal cant1: integer range 0 to 2**(7);
begin cant1 <= conv_integer(unsigned(dif));
b(7) <= a(7);
l1:for i in 0 to 6 generate
     b(i) <= a(i+cant1) when (i+cant1) < 7
     else '0';
   end generate;
end behavior;
